//https://hdlbits.01xz.net/wiki/Tb/https://hdlbits.01xz.net/wiki/Tb/tff
module top_module ();
	reg clk;
    reg reset;
    reg t;
    wire q;
    
    initial 
        begin
            clk = 0;
            forever 
            #5 clk = ~clk;
        end
        
    initial
        begin
            reset=1; t=0;
        #20 reset=0; t=1;
        end
    
    tff my_tff(.clk(clk), .reset(reset), .t(t), .q(q));
    
endmodule
/*
module tff (
    input clk,
    input reset,   // active-high synchronous reset
    input t,       // toggle
    output q
);
*/